View SC4612H_9072151.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 www.semtech.com sc46 1 2h 40v synchronous buck controller power management description features applications typical application circuit u wide input voltage range, 4.75v to 40v u internally regulated drv u 1.7a gate drive capability u low side r ds-on sensing with hiccup ocp u programmable current limit u programmable frequency up to 1.2 mhz u overtemperature protected u pre-bias startup u reference accuracy 1% u available in mlpd-12 4 x 3 and soic-14 pb-free packages. this product is fully weee and rohs compliant SC4612H is a high performance synchronous buck controller that can be configured for a wide range of applications. the SC4612H utilizes synchronous rectified buck topology where high efficiency is the primary consideration. SC4612H can be used over a wide input voltage range with output voltage adjustable within limits set by the duty cycle boundaries. SC4612H comes with a rich set of features such as regulated drv supply, programmable soft-start, high current gate drivers, shoot through protection, r ds-on sensing with hiccup over current protection. u distributed power architectures u telecommunication equipment u servers/work stations u mixed signal applications u base station power management u point of use low voltage high current applications revision: august 14, 2008 q1 q2 l1 c8 c10 + _ + _ vin vout r2 r4 c5 r1 adj c1 c9 c2 r5 c3 d1 c7 c4 ilim 1 phase 12 osc 2 ss/en 3 fb 5 vdd 6 gnd 7 dl 8 drv 9 bst 10 dh 11 eao 4 u1 sc4612mlp r3 opt r6 c6 c11 cin
2 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management absolute maximum ratings all voltages with respect to gnd. positive currents are into, and negative currents are out of the specified terminal. pulsed is defined as a less than 10% duty cycle with a maximum duration of 500ns. consult packaging section of data sheet for thermal limitations and considerations of packages. exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of the parameters specified in the electrical characteristics section is not implied. note: (1). thetaja is calculated from a package in still air, mounted to a 3? x 4.5?, 4 layer fr4pcb with thermal vias (if applicable) per jesd51 standards. parameter symbol maximum units bias supply voltage to gnd vdd -0.3 to 45 v phase to gnd vin -2 to +55 v drv, ilim, dl to gnd, bst, dh to phase -0.3 to 10 v eao, ss/en, fb, osc to gnd -0.3 to +5 v drv source current (peak) 100 ma thermal resistance junction to ambient (mlpd) (1) q ja 45.3 c/w thermal resistance junction to case (mlpd) q jc 11 c/w thermal resistance junction to ambient (soic) (1) q ja 115 c/w thermal resistance junction to case (soic) q jc 45 c/w storage temperature range t stg -65 to +150 c peak ir reflow temperature (10-40s) t ir reflow 260 c lead temperature (10s), (soic-14) t lead 300 c parameter symbol conditions min typ max units supply voltage range vdd 5 40 v ambient temperature range t a -40 105 o c junction temperature range t j -40 125 o c recommended operating condi tions performance is not guaranteed if the conditions below are exceeded.
3 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management vin = vdd = 12v, f osc = 600khz, t a = t j = 25 c. unless otherwise specified: parameter test conditions min typ max units bias supply quiescent current v dd = 40v, no load, ss/en = 0 5 7 ma vdd undervoltage lockout start threshold 4.20 4.50 4.75 v uvlo hysteresis 400 mv drive regulator drv 10v v dd 40v, i out 1ma 7.3 7.8 8.3 v load regulation 1ma i out 70ma 100 mv oscillator operation frequency range 100 1200 khz initial accuracy (1) c osc = 160pf (ref only) 540 600 660 khz maximum duty cycle v dd = v dr = 8v; v out_nom = 5v; i out = 0a v in adjust down to v out = 0.99 v out _nom 82 % ramp peak to valley (1) 850 mv oscillator charge current v osc = 1v 90 110 a current limit (low side rdson) current limit threshold voltage see pg. 12 & 13 on ocp 100 mv error amplifier feedback voltage t j = 0 to +70c 0.495 0.500 0.505 v t j = -40 to +85c 0.492 0.500 0.508 v t j = -40 to +125c 0.488 0.500 0.512 v input bias current fb = 0.5v 200 na open loop gain (1) 60 db unity gain bandwidth (1) 7 10 mhz output sink current open loop, fb = 0v 900 a output source current open loop, fb = 0.6v 1100 a slew rate (1) 1 v/s electrical characteristics
4 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management parameter test conditions min typ max units ss/en disable threshold voltage 500 mv soft start charge current 25 a soft start discharge current (1) 1 a disable low to shut down (1) 50 ns hiccup hiccup duty cycle c ss = 0.1, current limit condition 1 % gate drive gate drive on-resistance (h) (2) i source = 100ma 3 4 w gate drive on-resistance (l) (2) i sink = 100ma 3 4 w dl source/sink peak current (2) cout = 2000pf 1.4 1.7 a dh source/sink peak current (2) cout = 2000pf 1.4 1.7 a output rise time (2) cout = 2000pf 20 ns output fall time (2) cout = 2000pf 20 ns minimum non-overlap (1) 30 ns minimum on time (2) 110 ns thermal shutdown shutdown temperature (2) 165 c thermal shutdown hysteresis (2) 15 c electrical characteristics (cont.) unless otherwise specified: notes: (1) guaranteed by design. not production tested. (2) guaranteed by characterization. (3) this device is esd sensitive. use of standard esd handling precautions is required. vin = vdd = 12v, f osc = 600khz, t a = t j = 25 c.
5 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management part number (3) package (2) temp. range (t j ) SC4612Hmltrt mlpd-12 4 x 3 -40c to +125c SC4612Hstrt soic-14 SC4612Hevb (1) evaluation board pin configurations ordering information notes: (1) when ordering please specify mlpd or soic package. (2) only available in tape and reel packaging. a reel contains 3000 devices for mlpd package and 2500 for soic package.. (3) pb-free product. this product is fully weee and rohs compliant. 1 2 3 4 5 6 7 phase ilim top view (12 pin mlpd) 12 8 dh osc bst ss/en drv eao dl fb gnd vdd 10 9 11 nnnn = part number (example: 1531) yyww = date code (example: 0012) xxxxx = semtech lot no. (example:e9010) 1 2 3 4 5 6 7 phase nc top view (14 pin soic) 13 12 14 11 10 dh ilim bst osc drv ss/en dl eao gnd vdd fb nc 9 8 top mark 4612h yyww xxxxx marking information - mlpd nnnn = part number (example: SC4612H) yyww = date code (example: 0752) xxxxx = semtech lot no. (example:a01e90101) top mark marking information - soic SC4612H yyww xxxxxxxxx
6 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management pin descriptions pin # mlpd pin# soic pin name pin function 1, 7 nc no connection. 1 2 ilim the current limit programing resistor at this pin in conjunction with an internal current source programs the current limit threshold for the low side mosfet r ds-on sensing. once the voltage drop across the bottom mosfet is larger than the programmed value, current limit condition occurs, and the hiccup current limit protection is activated. 2 3 osc oscillator frequency set pin. an external capacitor to gnd will program the oscillator frequency. see table 1 "frequency vs. c osc " to determine oscillator frequency. 3 4 ss/en soft start pin. internal current source connected to a single external capacitor will determine the soft-start duration for the output. inhibits the chip if pulled down. 4 5 eao error amplifier output. a compensation network is connected from this pin to fb. 5 8 fb the inverting input of the error amplifier. feedback pin is used to sense the output voltage via a resistive divider. 6 6 vdd bias supply. also, vdd pin is internally used to provide the base drive to the internal pass transistor regulating the drv supply. 7 9 gnd ground. 8 10 dl drive low. gate drive for bottom mosfet. 9 11 drv drv supplies the external mosfets gate drive and the chips internal circuitry. this pin should be bypassed with a ceramic capacitor to gnd. drv is internally regulated from the external supply connected to vdd. if vdd is below 10v, the supply should be directly connected to the drv pin. 10 12 bst bst signal. supply for high side driver; can be directly connected to an external supply or to a bootstrap circuit. 11 13 dh drive high. gate drive for top mosfet. 12 14 phase the return path for the high side gate drive, also used to sense the voltage at the phase node for adaptive gate drive protection and the low-side r ds-on current sensing. x n/a thermal pad (gnd) pad for heatsinking purposes. connect to ground plane using multiple vias. ss ss ss i 2 . 1 x c t ?
7 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management block diagram s r q drv co _ int en drv dh bst osc otp s r q s r q osc osc splse vdd vref drv vref vss reg & bg vref v + v - ss _ 3 out - + drv s r q oc oc detect ssdn ssint sslo ss sshi softstart s r q s r q s r q + - s r q d d phase gnd s _ mod 830 mv + - 12 k ovp 0 . 6 v vdd ss / en fb ilim dl eao
8 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management typical characteristics typical soft start current vs temperature 22 23 24 25 -50 0 50 100 150 temperature ( o c) ss current (ua) typical error amp output current vs temperature -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 -50 0 50 100 150 temperature ( o c) i eao (ma) source; v eao =0v; v fb =0v sink; v eao =1.5v; v fb =0.6v typical drv voltage vs load current 25c -40c 125c 5 6 7 8 0 20 40 60 80 100 120 140 idrv (ma) vdrv (v) typical uvlo vs temperature vdd rising vdd falling 4.0 4.1 4.2 4.3 4.4 4.5 -50 0 50 100 150 temperature ( o c) undervoltage trip (v) typical vfb vs temperature vdd=5v vdd=42v 497 498 499 500 501 502 503 -50 0 50 100 150 temperature ( o c) vfb (mv) typical oscillator charge current vs temperature 94 96 98 100 102 104 -50 0 50 100 150 temperature ( o c) i osc (ua)
9 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management typical characteristics (cont.) typical vdd quiescent current vs temperature vdd=42v vdd=12v 0 1 2 3 4 5 -50 0 50 100 150 temperature ( o c) iq (ma) start up from vout = 0v start up from vout = 2.5v start up from vout = 2.5v first dh/dl pulses short circuit applied steady state waveforms
10 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management applications information introduction the SC4612H is a versatile voltage mode synchronous rectified buck pwm convertor, with an input supply (vin) ranging from 4.5v to 40v designed to control and drive n-channel mosfets. the power dissipation is controlled by allowing high speed and integration with the high drive currents to ensure low mosfet switching loss. the synchronous buck configu- ration also allows converter sinking current from load with- out losing output regulation. the internal reference is trimmed to 500mv with 1% accuracy, and the output voltage can be adjusted by an external resistor divider. a fixed oscillator frequency (up to 1.2mhz) can be programmed by an external capacitor for design optimization. other features of the SC4612H include: wide input power voltage range (from 4.5v to 40v), low output voltages, externally programmable soft-start, hiccup over current protection, wide duty cycle range, thermal shutdown, and -40 to 125c junction operating temperature range. theory of operation supplies two pins (vdd and drv) are used to power up the SC4612H. if input supply (vin) is less than 10v, tie drv and vdd together. this drv supply should be bypassed with a low esr 2.2uf (or greater) ceramic capacitor directly at the drv to gnd pins of the SC4612H. the drv supply also provides the bias for the low and the high side mosfet gate drive. the maximum rating for drv supply is 10v and for applications where input supply is below 10v, it should be connected directly to vdd. the internal pass transistor will regulate the drv from an external supply connected to vdd to produce 7.8v typical at the drv pin. soft start / shut down the SC4612H performs a ?pre-bias? type startup. this ensures that a pre-charged output capacitor will not cause the SC4612H to turn on the bottom fet during startup to discharge it, as a normal synchronous buck controller would do. an external capacitor on the ss/en pin is used to set the soft start duration. 6 ss ss 10 25 c 5 . 0 t - ? startup is inhibited until vdd input reaches the uvlo threshold (typically 4.5v). once vdd rises above uvlo, the external soft start capacitor begins to charge from an internal 25ua current source. when the ss/en pin reaches approximately 0.8v, top side switching is enabled. however, a top side pulse will not occur until ss/en has charged up to the level appropriate for the existing output voltage (a pre bias condition). once the first top side gate pulse actually occurs, the bottom side driver is enabled and the remainder of the startup is fully synchronous. in the event of an over current during startup, the SC4612H behaves in the same manner as an over current in steady state (see over current protection). oscillator frequency selection the internal oscillator sawtooth signal is generated by charging an external capacitor with a current source of 100 a charge current. see table 1 ?frequency vs. c osc ? to determine oscillator frequency. frequency, vs. c osc 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 frequency, (khz) cosc, (pf) table 1
11 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management applications information (cont.) under voltage lock out under voltage lock out (uvlo) circuitry senses the vdd through a voltage divider. if this signal falls below 4.5v (typical) with a 400mv hysteresis (typical), the output driv- ers are disabled. during the thermal shutdown, the out- put drivers are disabled. overcurrent protection the SC4612H features low side mosfet r ds(on) current sensing and hiccup mode over current protection. the voltage across the bottom fet is sampled approximately 150ns after it is turned on to prevent false tripping due to ringing of the phase node. the internally set over current threshold is 100mv typical. this can be adjusted up or down by connecting a resistor between ilim and drv or gnd respectively. when programming with an external resistor, threshold set point accuracy will be degraded to 30%. the fet r ds(on) at temperature will typically be 150% or more of the room temperature value. allowance should be made for these sources of error when programming a threshold value. when an over current event occurs, the SC4612H immediately disables both gate drives. the ss ramp continues to its final value, if not already there. once at final value, the ss capacitor is discharged at approximately 1ua until ss low value is reached (approx 0.8v). the ss/ hiccup cycle will then repeat until the fault condition is removed and the SC4612H starts up normally on the next ss cycle. gate drive/control the SC4612H provides integrated high current drivers for fast switching of large m osfet s. the higher gate current will reduce switching losses of the larger mosfets. the low side gate drive is supplied directly from the drv. the high side gate drive is bootstraped from the drv pin. cross conduction prevention circuitry ensures a non over- lapping (30ns typical) gate drive between the top and bot- tom m osfets . this prevents shoot through losses which provides higher efficiency. typical total minimum off time for the SC4612H is about 30ns. error amplifier design the SC4612H is a voltage mode buck controller that utilizes an externally compensated high bandwidth error amplifier to regulate the output voltage. the power stage of the synchronous rectified buck converter control-to-output transfer function is as shown below. ? ? ? ? ? ? ? ? + + + = lc 2 s l r l s 1 c c sesr 1 s v in v ) s ( vd g where, v in ? input voltage l ? output inductance esr c ? output capacitor esr v s ? peak to peak ramp voltage r l ? load resistance c ? output capacitance the classical type iii compensation network can be built around the error amplifier as shown below: r3 c3 r2 r1 c1 vref c2 - + figure 1. voltage mode buck converter compensation network. the transfer function of the compensation network is as follows: ) s 1 )( s 1 ( ) s 1 )( s 1 ( s ) s ( g 2 p 1 p 2 z 1 z i comp w + w + w + w + w = where, cout lout 1 , c ) r r ( 1 , c r 1 o 2 3 1 2 z 1 2 1 z = w + = w = w 3 1 3 1 2 2 p 2 3 1 p 3 1 1 i c c c c r 1 , c r 1 , ) c c ( r 1 + = w = w + = w
12 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management the design guidelines are as following: 1. set the loop gain crossover frequency w c for given switching frequency. 2. place an integrator at the origin to increase dc and low frequency gains. 3. select w z1 and w z2 such that they are placed near w o to dampen peaking; the loop gain should cross 0db at a rate of -20db/dec. 4. cancel w esr with compensation pole w p1 (w p1 = w esr ). 5. place a high frequency compensation pole w p2 at half the switching frequency to get the maximum attenuation of the switching ripple and the high frequency noise with adequate phase lag at w c . 0db gd t w z1 w z2 p1 p2 c esr w o w w w w loop gain t(s) figure 2. simplified asymptotic diagram of buck power stage and its compensated loop gain. applications information (cont.)
13 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management component selection: switching section output capacitors - selection begins with the most critical component. because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. output capacitor esr is therefore one of the most important criteria. the maximum esr can be simply calculated from: step current transient i excursion voltage transient maximum v where i v r t t t t esr = = for example, to meet a 100mv transient limit with a 10a load step, the output capacitor esr must be less than 10m w . to meet this kind of esr level, there are three available capacitor technologies. technology each capacitor qty rqd. total c (uf) esr (m w ) c (uf) esr (m w ) ceramic 22 2-10 1 22 2-10 sp cap 220 7 1 220 7.0 pos-cap 680 18 2 1360 9.0 low esr aluminum 1500 44 5 7500 8.8 the choice of which to use is simply a cost/performance issue, with low esr aluminum being the cheapest, but taking up the most space. inductor - having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the esr excursion calculated above. the maximum inductor value may be calculated from: ( ) o in t esr v v i c r l - the calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the esr at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. we must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor esr. ripple current can be calculated from: osc in l f l 4 v i ripple = ripple current allowance will define the minimum permitted inductor value. power fets - the fets are chosen based on several criteria with probably the most important being power dissipation and power handling capability. top fet - the power dissipation in the top fet is a combination of conduction losses, switching losses and bottom fet body diode recovery losses. a) conduction losses are simply calculated as: in o ) on ( ds 2 o cond v v cycle duty = d where d r i p ? = b) switching losses can be estimated by assuming a switching time, if we assume 100ns then: sw in o sw t ns 100 v i p = or more generally, 2 f ) t t ( v i p osc f r in o sw + = c) body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume application information (cont.)
14 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management low side r ds_on current limit 1. programming resistors ra and rb - not installed: 2 r vphase mv 100 3 r mv 100 v 75 . 2 - = - solving for: v phase = -100mv, therefore the circuit will trip @ r ds_on x i load = 100mv 2. to increase trip voltage - install ra. phase phase v 10 1 v 20 772 ra + - - = solving for double the current limit: v phase = -200mv. ra = 768k w . 3. to decrease trip voltage - install rb phase phase v 10 1 v 20 8 rb + - = solving for half the current limit: v phase = -50mv. rb = 18k w . note! allow for tempco and r ds_on variation of the mos- fet - see ?overcurrent protection? information on page 11 in the datasheet. that the stored charge on the bottom fet body diode will be moved through the top fet as it starts to turn on. the resulting power dissipation in the top fet will be: osc in rr rr f v q p = bottom fet - bottom fet losses are almost entirely due to conduction. the body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the fet turns on and off, there is very little voltage across it resulting in very low switching losses. conduction losses for the fet can be determined by: ) d 1 ( r i p ) on ( ds 2 o cond - = input capacitors - since the rms ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. also, during fast load transients, there may be restrictions on input di/dt. these restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. choosing low esr input capacitors will help maximize ripple rating for a given size. application information (cont.)
15 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management application information (cont.) application circuit 1: vin = 24v; vout = 3.3v @ 20a, fsw = 500khz. vin=24v, vout_nom=3.3v, fsw=500khz 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 2 4 6 8 10 12 14 16 18 20 current, (a) efficiency q1 q2 l1 1.5uh c8 0.1 c10 180/4v + _ + _ vin=24v vout=3.3@20a r2 10k r4 6.98k c5 1 r1 adj c1 200p c9 c2 0.1 r5 39.2k c3 3.9n d1 mbr0530 c7 2.2 c4 300p ilim 1 phase 12 osc 2 ss/en 3 fb 5 vdd 6 gnd 7 dl 8 drv 9 bst 10 dh 11 eao 4 u1 sc4612mlp r3 10 r6 887 c6 750p c13 10/6.3v c11 180/4v fsw=500khz c12 180/4v c15 470/35v c14 470/35v
16 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management application information (cont.) application circuit 2: vin = 12v; vout = 3.3v @ 10a, fsw = 1mhz vin=12v, vout_nom=3.3v, fsw=1mhz 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 1 2 3 4 5 6 7 8 9 10 current, (a) efficiency q1 q2 l1 1uh c8 0.1 c10 680/4v + _ + _ vin=12v vout=3.3@10a r2 13.7k r4 3.83k c5 1 r1 adj c1 82p c9 c2 0.1 r5 21.5k c3 2.7n d1 mbr0520 c7 2.2 c4 1n ilim 1 phase 12 osc 2 ss/en 3 fb 5 vdd 6 gnd 7 dl 8 drv 9 bst 10 dh 11 eao 4 u1 sc4612mlp r3 10 r6 267 c6 1.2n c11 10 fsw=1000khz c12 220/16v
17 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management application information (cont.) application circuit 3: vin = 5v; vout = 1.25v @ 12a, fsw = 1mhz. vin=5v, vout_nom=1.25v, fsw=1mhz 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 1 2 3 4 5 6 7 8 9 10 11 12 13 current, (a) efficiency q1 q2 l1 0.47uh c8 0.1 c10 100/4v + _ + _ vin=5v vout=1.25@12a r2 10k r4 8.87k c5 1 r1 adj c1 82p c9 c2 0.1 r5 13.3k c3 1n d1 sd107ws c7 2.2 c4 33p ilim 1 phase 12 osc 2 ss/en 3 fb 5 vdd 6 gnd 7 dl 8 drv 9 bst 10 dh 11 eao 4 u1 sc4612mlp r3 0 r6 649 c6 510p c11 1 fsw=1000khz c12 100/6.3v
18 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management application information (cont.) evaluation board: top layer and components view bottom layer:
19 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management pcb layout guidelines careful attention to layout is necessary for successful implementation of the SC4612H pwm controller. high switching currents are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1) the high power section of the circuit should be laid out first. a ground plane should be used. the number and position of ground plane interruptions should not unnecessarily compromise ground plane integrity. isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas; for example, the input capacitor and bottom fet ground. 2) the loop formed by the input capacitor(s) (cin), the top fet (m1), and the bottom fet (m2) must be kept as small as possible. this loop contains all the high current, fast transition switching. connections should be as wide and as short as possible to minimize loop inductance. minimizing this loop area will a) reduce emi, b) lower ground injection currents, resulting in electrically ?cleaner? grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3) the connection between the junction of m1, m2 and the output inductor should be a wide trace or copper region. it should be as short as practical. since this connection has fast voltage transitions, keeping this connection short will minimize emi. also keep the phase connection to the ic short. top fet gate charge currents flow in this trace. 4) the output capacitor(s) (cout) should be located as close to the load as possible. fast transient load currents are supplied by cout only, and therefore, connections between cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) the SC4612H is best placed over a quiet ground plane area. avoid pulse currents in the cin, m1, m2 loop flowing in this area. gnd should be returned to the ground plane close to the package and close to the ground side of (one of) the output capacitor(s). if this is not possible, the gnd pin may be connected to the ground path between the output capacitor(s) and the cin, m1, m2 loop. under no circumstances should gnd be returned to a ground inside the cin, m1, m2 loop. 6) allow adequate heat sinking area for the power components. if multiple layers will be used, provide sufficent vias for heat transfer. voltage and current waveforms of buck power stage . vout vin + + ids (top fet) ids (bottom fet) i (input capacitor) vphase i (inductor) vout i (output capacitor)
20 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management outline drawing - mlpd - 12 bxn e millimeters 0.50 bsc .002 .001 0.00 .000 a1 .114 .154 .061 .124 .012 .007 e1 aaa bbb n e l a2 d1 d e b .020 bsc .067 .016 .003 .004 12 .118 (.008) .130 .157 .010 - 1.55 .071 .020 0.30 .161 .122 .134 - .012 3.90 2.90 3.15 - 0.18 .031 min dim a max dimensions inches .035 nom .040 0.80 min 0.02 0.05 3.10 4.10 1.80 3.40 0.50 0.30 1.70 0.40 0.10 0.08 12 3.00 (0.20) 3.30 4.00 0.25 - 1.00 max 0.90 nom a b pin1 indicator (laser mark) a1 a aaa c a2 c seating plane 1 2 n bbb c a b coplanarity applies to the exposed pad as well as the terminals. controlling dimensions are in millimeters (angles in degrees). notes: 2. 1. d e d1/2 d1 e1/2 e1 lxn land pattern - mlpd - 12 this land pattern is for reference purposes only. consult your manufacturing group to ensure your notes: 1. dim x y h k p c g millimeters inches (2.90) .012 .028 .087 .020 .138 .067 (.114) 0.30 0.70 1.70 0.50 3.50 2.20 dimensions company's manufacturing guidelines are met. 3.60 .142 z
21 ? 2008 semtech corp. www.semtech.com sc46 1 2h power management semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 contact information outline drawing - soic - 14 see detail detail a a .050 bsc .236 bsc 14 .010 .150 .337 .154 .341 .012 - 14 0.25 1.27 bsc 6.00 bsc 3.90 8.65 - .157 .344 3.80 8.55 .020 0.31 4.00 8.75 0.51 bxn 2x n/2 tips seating aaa c e/2 2x 3 a d a1 e1 bbb c a-b d ccc c a2 (.041) .004 .008 - .028 - - - - 0 .016 .007 .049 .004 .053 8 0 0.20 0.10 - 8 0.40 0.17 1.25 0.10 .041 .010 .069 .065 .010 1.35 (1.04) 0.72 - 1.04 0.25 - - - 1.75 1.65 0.25 0.25 - .010 .020 0.50 - c l (l1) 01 0.25 gage plane h h plane n 1 2 a e d c h b 3. dimensions "e1" and "d" do not include mold flash, protrusions or gate burrs. -b- controlling dimensions are in millimeters (angles in degrees). datums and to be determined at datum plane notes: 1. 2. -a- -h- side view reference jedec std ms-012, variation ab. 4. l1 ccc aaa bbb 01 n dim e1 d a1 a2 dimensions millimeters min e l h e b c inches nom min a max max nom e z g y p (c) x this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. reference ipc-sm-782a, rlp no. 302a. 2. .291 .087 .024 .118 (.205) inches dimensions z p y x dim c g millimeters .050 (5.20) 7.40 2.20 0.60 3.00 1.27 land pattern - soic - 14

▲Up To Search▲

Price & Availability of SC4612H

	To Download SC4612H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .